This invention relates to circuitry and methods for causing a signal to jitter, e.g., to facilitate testing of the jitter-tolerance of circuitry receiving the signal.
An example of circuitry that may need to be tested for jitter-tolerance is serializer/deserializer (SERDES) circuitry. SERDES circuitry may be used in a transmitter for converting data supplied as a succession of parallel words to a continuous stream of serial bits. Circuitry that receives this serial data signal may use another SERDES to recover the successive bits from the received signal and reassemble those bits into successive parallel words for further processing. Clock data recovery (CDR) techniques may be used as part this data recovery operation. (The term “words” is used herein to mean any plural number of bits that may be treated as a significant unit of information. For example, a word may be eight bits; but a word can also be any other plural number of bits such as ten bits or 16 bits. There is no special significance to the use of the term word herein, and other terms such as nibble, byte, or group could have been used instead with no change in scope or coverage.)
In real-world applications the serial data signal received by a receiver is rarely, if ever, perfect. One of its imperfections may be jitter. Jitter is variation in the timing of transitions in the binary level of the received signal. Such transitions should occur only at boundaries between unit intervals (UIs) in the data signal. A UI is the time duration of any one bit in the data signal. It is not necessary for the data signal to transition after each UI; but when a transition does occur, it should be at the end of one UI and the start of the next UI. Because the UI is a fixed amount of time, transitions in the received serial data signal should occur only at certain times relative to one another (i.e., integer multiples of the UI). This fact may be used by a SERDES to help it synchronize its operations (e.g., its data recovery operations) to the incoming serial data signal. However, jitter can cause the timing of transitions in the received data signal to deviate from proper timing. For example, jitter can cause a transition in the received data signal to be delayed by some fraction of a UI, or to occur earlier than it should by some fraction of a UI. A SERDES should be able to tolerate some amount of jitter without losing its ability to correctly recover received serial data.
Known automatic test equipment (ATE) for production testing is not well adapted to producing serial data signals with jitter to facilitate production testing of the jitter tolerance of SERDES or other receiver circuitry. It would therefore be desirable to provide circuitry and methods for facilitating the use of automatic test equipment to test the jitter tolerance of circuitry such as SERDES circuitry.